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I'm supposed to explain how the 0s and 1s in transitors are interpreted...

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MAlibdem Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 12:30 PM
Original message
I'm supposed to explain how the 0s and 1s in transitors are interpreted...
by a computer for my physics class. Like, how electrical signals are transferred into memory and used for calculations. Unfortunately, I don't really know where to start to look for info. I tried http://www.howstuffworks.com but their explanation lacks technical information which I need.

ANY help would be appreciated!
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LoZoccolo Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 12:39 PM
Response to Original message
1. digital logic
Edited on Sat May-15-04 12:40 PM by LoZoccolo
The "combinational logic" part should be of help here:

http://www.play-hookey.com/digital
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LoZoccolo Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 12:42 PM
Response to Original message
2. arithmetic and logic unit
This is the part of the CPU that calculates results based on the signals it gets:

http://www2.ele.ufes.br/~ailson/digital2/cld/chapter5/c...
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TrogL Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 12:43 PM
Response to Original message
3. Leading edges
I'm not quite sure if I'm answering the right question, but computer chips sense the leading edge as a voltage switches (eg. in older chips) from 0 to 5 volts rather than the voltage itself. The computer works on a constant stream of changing voltages synced by a timing circuit (in the early days, a 555 chip).

A CPU has a number of data streams on separate channels (called busses). Often these busses are shared for different purposes based upon what's going on at the time. In the old days there was an address bus, an I/O bus and a data buss shared by several processes. In newer chips, this distinction is blurred.

Memory is a raster/grid of on/off switches. On a memory write, the memory management unit receives a signal from the processor warning it about an incoming stream. The stream consists of the address (probably on the address bus) followed by the data (on the data bus). The MMU coordinates setting the correct grid with the appropriate voltages. In the case of a read, the MMU is warned of a read, receives the addresses required, then dumps the memory stream on the address and data busses. The CPU senses the edges (or lack of them) of the incoming stream and proceeds appropriately.

I/O is handled in a similar manner.

Does that help?
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LoZoccolo Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 12:45 PM
Response to Original message
4. flip-flops
I couldn't find anything good in the time I have but for memory, try looking in the direction of "flip-flops" and "set/reset latches".
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Trajan Donating Member (1000+ posts) Send PM | Profile | Ignore Sat May-15-04 01:03 PM
Response to Original message
5. You use the word 'Transitors' ...
Did you mean Transistors ? ... or Transitions ? ...

Either could be relevent ...

Anyways, Lo is on the right track, I think ...

"Transistors" are used as logic storage devices by placing them into one of two states: cut off or saturation ...

Cut off is a x-istor turned off: The reversed biased B-E junction causes the emitter to block charge carriers from entering the base and collector .... the collector voltage = Vcc (high) ....

This becomes a '1' in positive logic systems


Saturation is a x-sistor turned on: the forward biased b-e region draws charge carriers into the base and collector ... it is full on, with little resistance between the Emitter and Collector ... the collector voltage = Vee ... IE Ground or o volts ...

This becomes a '0' in positive logic systems

Now; to follow up with another poster: xistors can be configured into a 'latch' .... one main configuration is called the 'bistable multivibrator', 'bistable latch' or 'flip flop' .... they are stable at either the HIGH state or the LOW state .... hence they can 'store' either a 1 or 0 ....

8 flip flops placed side to side can store 8 bits, or 1 BYTE of data ...

Those 8 flip flops can be cascaded as well ....

1024 groups of 8 such flip flops (with address select logic) would be a '1K x 8' memory ....

I hope this helps a not hinders ...

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